The use of high speed data transfer circuitry continues to expand as electrical and electronic devices handling large amounts of data proliferate. One example of such high speed data transfer circuitry is a parallel in, serial out data serializer. Data serializers, as well as other high speed data transfer circuitry, are prone to introduce inter symbol interference (“ISI”) into the data stream. The presence of ISI typically reduces the data transfer capability of a system as it leads to an increase in bit error rate and/or increased jitter.
In typical high speed data serializers, a serial stream of binary data bits is produced where each data bit has a signal level which represents a logical “1” (or “high”) or a logical “0” (or “low”). However, when consecutive bits in the serial stream have different logic levels, e.g., a first bit represents a logical low (nominally, a 0) and the next bit represents a logical high (nominally, a 1), or vice-versa, the actual signal level in the high speed data transfer circuit may not rise or fall to the appropriate nominal value. Thus, inter symbol interference may be induced in the data bit stream.
Thus, there is a need for circuitry and/or method to reduce inter symbol interference.